EDSEL=OFF, SOURCESEL=NONE
Channel Control Register
| SIGSEL | Signal Select |
| SOURCESEL | Source Select 0 (NONE): No source selected 1 (PRSL): Peripheral Reflex System 2 (PRSH): Peripheral Reflex System 3 (ACMP0): Analog Comparator 0 4 (ACMP1): Analog Comparator 1 5 (ADC0): Analog to Digital Converter 0 7 (LESENSEL): Low Energy Sensor Interface 8 (LESENSEH): Low Energy Sensor Interface 9 (LESENSED): Low Energy Sensor Interface 10 (LESENSE): Low Energy Sensor Interface 11 (RTCC): Real-Time Counter and Calendar 12 (GPIOL): General purpose Input/Output 13 (GPIOH): General purpose Input/Output 14 (LETIMER0): Low Energy Timer 0 15 (PCNT0): Pulse Counter 0 16 (PCNT1): Pulse Counter 1 17 (PCNT2): Pulse Counter 2 18 (CMU): Clock Management Unit 24 (VDAC0): Digital to Analog Converter 0 26 (CRYOTIMER): CRYOTIMER 48 (USART0): Universal Synchronous/Asynchronous Receiver/Transmitter 0 49 (USART1): Universal Synchronous/Asynchronous Receiver/Transmitter 1 50 (USART2): Universal Synchronous/Asynchronous Receiver/Transmitter 2 51 (USART3): Universal Synchronous/Asynchronous Receiver/Transmitter 3 60 (TIMER0): Timer 0 61 (TIMER1): Timer 1 62 (WTIMER0): Wide Timer 0 63 (WTIMER1): Wide Timer 1 67 (CM4): undefined |
| EDSEL | Edge Detect Select 0 (OFF): Signal is left as it is 1 (POSEDGE): A one HFCLK cycle pulse is generated for every positive edge of the incoming signal 2 (NEGEDGE): A one HFCLK clock cycle pulse is generated for every negative edge of the incoming signal 3 (BOTHEDGES): A one HFCLK clock cycle pulse is generated for every edge of the incoming signal |
| STRETCH | Stretch Channel Output |
| INV | Invert Channel |
| ORPREV | Or Previous |
| ANDNEXT | And Next |
| ASYNC | Asynchronous Reflex |